IEEE 488.2 Common Commands

Standard Event Register

The following table describes the Standard Event Register.

Bit Number	Bit Name	Decimal Value	Definition
0	Operation Complete	1	All commands prior to and including *OPC have been executed.
1	Not Used	2	0 is returned.
2	Query Error	4	The instrument tried to read the output buffer but it was empty. Or, a new command line was received before a previous query has been read. Or, both the input and output buffers are full.
3	Device-Specific Error	8	A device-specific error, including a self-test error or calibration error, occurred (an error in the -300 range or any positive error has been generated). See SCPI Error Messages for the complete SCPI error message list.
4	Execution Error	16	An execution error occurred (an error in the -200 range has been generated).
5	Command Error	32	A command syntax error occurred (an error in the -100 range has been generated).
6	Not Used	64	0 is returned.
7	Power On	128	Power has been cycled since the last time the event register was read or cleared.

Status Byte Register

The following table describes the Status Byte Register.

Bit Number	Bit Name	Decimal Value	Definition
0	Not Used	1	(Reserved for future use)
1	Not Used	2	(Reserved for future use)
2	Error Queue	4	One or more errors have been stored in the Error Queue. Use SYSTem:ERRor? to read and delete errors.
3	Questionable Data Summary	8	One or more bits are set in the Questionable Data Register (bits must be enabled, see STATus:QUEStionable:ENABle).
4	Message Available	16	Data is available in the instrument's output buffer.
5	Standard Event Summary	32	One or more bits are set in the Standard Event Register (bits must be enabled, see *ESE).
6	Master Summary	64	One or more bits are set in the Status Byte Register and may generate a Request for Service (RQS). Bits must be enabled using *SRE.
7	Standard Operation Summary	128	One or more bits are set in the Standard Operation Register (bits must be enabled, see STATus:OPERation:ENABle).

*CLS

Clear Status Command. Clears the event registers in all register groups. Also clears the error queue.

Parameter	Typical Return
(none)	(none)
Clear event register bits and error queue: *CLS

*ESE <enable_value>
*ESE?

Event Status Enable Command and Query. Enables bits in the enable register for the Standard Event Register group. The selected bits are then reported to bit 5 of the Status Byte Register. An enable register defines which bits in the event register will be reported to the Status Byte register group. You can write to or read from an enable register.

For more information on the SCPI Status System, see Status Subsystem Introduction.

Parameter	Typical Return
Decimal sum of the bits in the register, default 0. For example, to enable bit 2 (value 4), bit 3 (value 8), and bit 7 (value 128), the decimal sum would be 140 (4 + 8 + 128). Default 0.	+48
Configure 100 DC voltage measurements and enable the generation of an SRQ when the measurements complete: *CLS *ESE 1 *SRE 32 CONF:VOLT:DC SAMP:COUN 100 INIT *OPC

• Use *PSC to control whether the Standard Event enable register is cleared at power on. For example, *PSC 0 preserves the enable register contents through power cycles.
• *CLS clears the event register, but not the enable register.

• The <enable> setting is nonvolatile; it does not change after a Factory Reset (*RST) , Instrument Preset (SYSTem:PRESet), Status Preset (STATus:PRESet) or Clear Status (*CLS).

*ESR?

Standard Event Status Register Query. Queries the event register for the Standard Event Register group.

An event register is a read-only register that latches events from the condition register. While an event bit is set, subsequent events corresponding to that bit are ignored.

Parameter	Typical Return
(none)	+24
Read the event register (bits 3 and 4 are set). *ESR?

• In order to be reported to the Status Byte Register, the corresponding bits in the enable register must be enabled by *ESE.
• Any or all conditions can be reported to the Standard Event summary bit through the enable register. To set the enable register mask, write a decimal value to the register using *ESE.
• Once a bit is set, it remains set until cleared by reading the event register or by sending *CLS (clear status).

*IDN?

Identification Query. Returns the instrument’s identification string.

Parameter	Typical Return
(none)	(see below)
Return the instrument's identification string: *IDN?

• The identification string contains four comma separated fields:
  
  Manufacturer name, Model number, Serial number, Revision code
  
  If SYSTem:IDENtify DEFault is set, the returned string has the following format:
  Agilent Technologies,34460A,<Serial Number>,ff.ff-pp.pp-mm.mm-gg.gg-bb-pp
  Agilent Technologies,34461A,<Serial Number>,ff.ff-pp.pp-mm.mm-gg.gg-bb-pp
  
  If SYSTem:IDENtify HP34401A is set, the returned string has the following format:
  HEWLETT-PACKARD,34401A,<Serial Number>,ff.ff-pp.pp-mm.mm-gg.gg-bb-pp
  
  Where:

ff.ff	Main firmware revision
pp.pp	Front panel firmware revision
mm.mm	Measurement board firmware revision
gg.gg	Measurement board FPGA revision
bb	Measurement board revision
pp	Front panel board revision

*LRN?

Returns an ASCII string of all of the commands required to put the instrument into its current state.

Parameter	Typical Return
(none)	An ASCII string of SCPI commands, delimited with semicolons (";") between commands.
Return the learn string: *LRN?

• Some parameters can be set with either [SENSe:]FREQuency or [SENSe:]PERiod versions of the same command. The *LRN string will always return the FREQuency version of the command, even if the parameter was set via the PERiod version. Similarly, parameters that can be set with RESistance or FRESistance versions of the same command will always return the FRESistance version.

*OPC

Sets "Operation Complete" (bit 0) in the Standard Event register at the completion of the current operation.

Parameter	Typical Return
(none)	(none)
Configure 100 DC voltage measurements and enable the generation of an SRQ when the measurements complete: *CLS *ESE 1 *SRE 32 CONF:VOLT:DC SAMP:COUN 100 INIT *OPC

• Other commands may be executed before Operation Complete bit is set.
• The difference between *OPC and *OPC? is that *OPC? outputs "1" when the current operation completes.

*OPC?

Returns 1 to the output buffer after all pending commands complete. Other commands cannot be executed until this command completes.

Parameter	Typical Return
(none)	1
Configure 100 DC voltage measurements and return "1" when the measurements complete: CONF:VOLT:DC SAMP:COUN 100 INIT *OPC?

• The purpose of this command is to synchronize your application with the instrument.
• The difference between *OPC and *OPC? is that *OPC? outputs "1" when the current operation completes.

*OPT?

Returns a string identifying any installed options.

Parameter	Typical Return
(none)	(see below)
Return the installed options: *OPT?

• The query returns a string with the following format:
  
  34460A: {GPB|0},{LAN|0},{SEC|0}
  34461A: {GPB|0},{SEC|0}
  
  In each case, the option is returned as 0 (not installed) or as GPB, LAN, or SEC.
  
  For example, a 34461A with only GPIB installed will return GPB,0. A 34460A with only GPB and SEC installed will return GPB,0,SEC.
• Options vary by model, as shown here.

*PSC {0|1}
*PSC?

Power-On Status Clear. Enables (1) or disables (0) the clearing of certain enable registers at power on:

• Questionable Data Register (STATus:QUEStionable:ENABle)
• Standard Operation Register (STATus:OPERation:ENABle)
• Status Byte Condition Register (*SRE)
• Standard Event Enable Register (*ESE)

The *PSC command does not affect the clearing of the condition or event registers, just the enable registers. For more information on the SCPI Status System, see Status Subsystem Introduction.

Parameter	Typical Return
{0|1}, default 1	0 or 1
Disable power-on clearing of affected registers: *PSC 0

*RCL {0|1|2|3|4}
*SAV {0|1|2|3|4}

Stores the current instrument state to, or recalls the instrument state from, the state file STATE_<n>.sta in the root folder of the internal flash file system, where <n> is the number specified.

Parameter	Typical Return
{0|1|2|3|4}	(none)
Store the instrument state to the state file STATE_1.sta in the root folder of the internal flash file system. *SAV 1

• *SAV <n> is equivalent to MMEMory:STORe:STATe "INT:\STATE_n.sta".
• *RCL <n> is equivalent to MMEMory:LOAD:STATe "INT:\STATE_n.sta".
• The state file created by *SAV 0, called STATE_0.sta, resides in the root folder of the internal flash file system. It is overwritten with the power-down state of the instrument when power is cycled.
• The instrument state enable settings are stored in nonvolatile memory. They do not change when power has been off, after a Factory Reset (*RST) or after an Instrument Preset (SYSTem:PRESet).

*RST

Resets instrument to factory default state, independent of MMEMory:STATe:RECall:AUTO setting. This is similar to SYSTem:PRESet. The difference is that *RST resets the instrument for SCPI operation, and SYSTem:PRESet resets the instrument for front-panel operation. As a result, *RST turns the histogram and statistics off, and SYSTem:PRESet turns them on (CALC:TRAN:HIST:STAT ON).

Parameter	Typical Return
(none)	(none)
Reset the instrument: *RST

• Does not affect stored instrument states (see *SAV).

*SRE<enable_value>
*SRE?

Service Request Enable. Enables bits in the enable register for the Status Byte Register group. An enable register defines which bits in the event register will be reported to the Status Byte register group. You can write to or read from an enable register.

Parameter	Typical Return
Decimal sum of the bits in the register, default 0. For example, to enable bit 2 (value 4), bit 3 (value 8), and bit 7 (value 128), the decimal sum would be 140 (4 + 8 + 128). Default 0.	+24
Enable bits 3 and 4 in the enable register: *SRE 24

• To enable specific bits, specify the decimal value corresponding to the binary-weighted sum of the bits in the register. The selected bits are summarized in the "Master Summary" bit (bit 6) of the Status Byte Register. If any of the selected bits change from 0 to 1, the instrument generates a Service Request signal.
• *CLS clears the event register, but not the enable register. An event register is a read-only register that latches events from the condition register. While an event bit is set, subsequent events corresponding to that bit are ignored.
• *PSC (power-on status clear) determines whether Status Byte enable register is cleared at power on. For example, *PSC 0 preserves the enable register contents through power cycles.
• The Status Byte enable register is not cleared by *RST.

*STB?

Read Status Byte Query. Queries the condition register for the Status Byte Register group and returns a decimal value equal to the binary-weighted sum of all bits set in the register.

A condition register continuously monitors the state of the instrument. Condition register bits are updated in real time; they are neither latched nor buffered.

Parameter	Typical Return
(none)	+40
Read condition register (with bits 3 and 5 set): *STB?

• Similar to a Serial Poll, but processed like any other instrument command. This register is read-only; bits are not cleared when read.
• Returns same result as a Serial Poll, but the "Master Summary" bit (bit 6) is not cleared by *STB?.
• Power cycle and *RST clear all bits in the condition register.

*TRG

Triggers the instrument if TRIGger:SOURce BUS is selected.

Parameter	Typical Return
(none)	(none)
Return five DC voltage measurements, using a software trigger to start the measurements: CONF:VOLT:DC SAMP:COUN 5 TRIG:SOUR BUS INIT *TRG FETCH? Typical Response:+1.00520000E+01, … (5 measurements)

• After setting the trigger source, you must send INITiate to place the DMM in the "wait-for-trigger" state. The *TRG command will not be accepted unless the DMM is in the "wait-for-trigger" state.

*TST?

Performs a basic self-test of the instrument and returns a pass/fail indication. The TEST:ALL? self-test is more comprehensive than the *TST? self-test.

Parameter	Typical Return
(none)	+0 (pass) or +1 (one or more tests failed)
Perform self-test: *TST?

• The self-test takes just a few seconds to complete.
• If one or more tests fail, the query returns +1 and stores an error in the error queue. For a complete listing of the error messages related to self-test failures, see Self-test Error Messages.
• Following the test, the instrument returns to the instrument state that existed before the self-test.

*WAI

Configures the instrument's output buffer to wait for all pending operations to complete before executing any additional commands over the interface.

Parameter	Typical Return
(none)	(none)
Wait until all pending operations complete: *WAI

• Configuration changes and measurements are considered pending operations. Therefore, *WAI will cause these changes to occur and complete.