Overall
Status Byte Register System
Status Register Bit Values
Accessing Status Register Information
Status Byte Group
Status Groups
You can use the PXB’s status register system to monitor error conditions, or condition changes, or both. In general, the error queue is easier to use than the status registers, but the status registers provide some additional information not found in the error queue. Refer to the SCPI Status commands for querying registers.
The PXB’s status register system provides two major advantages:
You can monitor the settling of the PXB using the settling bit of the Standard Operation Status Group’s condition register.
You can use the service request (SRQ) interrupt technique to avoid status polling, therefore giving a speed advantage.
The PXB’s instrument status system provides complete SCPI compliant data structures for reporting instrument status using the register model. The SCPI register model of the status system has multiple registers that are arranged in a hierarchical order. The lower-priority status registers propagate their data to the higher-priority registers using summary bits. The Status Byte Register is at the top of the hierarchy and contains the status information for lower level registers. The lower level registers monitor specific events or conditions.
The lower level status registers are grouped according to their functionality. For example, the Frequency Questionable Status Group consists of five registers. This topic may refer to a group as a register so that the cumbersome longer description is avoided. For example, the Standard Operation Status Group’s Condition Register can be referred to as the Standard Operation Status register.
The graphic below shows the PXB’s status byte register system and hierarchy.
The status register systems use IEEE 488.2 commands (those beginning with *) to access the higher-level summary registers. Access lower-level registers by using Status System Commands.
Each bit in a register is represented by a decimal value based on its location in the register.
To enable a particular bit in a register, send its value with the SCPI command.
To enable more than one bit, send the sum of all the bits that you want to enable.
To verify the bits set in a register, query the register.
To enable bit 0 and bit 6 of the Standard Event Status Group’s Event Register:
Add the decimal value of bit 0 (1) and the decimal value of bit 6 (64) to give a decimal value of 65.
Send the sum with the command: *ESE 65.
To query a register for a condition, send a SCPI query command. For example, if you want to query the Standard Operation Status Group’s Condition Register, send the command:
STATus:OPERation:CONDition?
If bit 7, bit 3, and bit 2 in this register are set (bits = 1), then the query will return the decimal value 140 (128 + 8 + 4 = 140).
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Bit 15 is not used and is always set to zero. |
Determine which register contains the bit that reports the condition. Refer to the status register graphics for register location and names.
Send the unique SCPI query that reads that register.
Examine the bit to see if the condition has changed.
You can monitor the following conditions:
current PXB hardware and firmware status
whether a particular condition (bit) has occurred
Monitoring Current PXB Hardware and Firmware Status
To monitor the PXB’s operating status, you can query the condition registers. These registers represent the current state of the PXB and are updated in real time. When the condition monitored by a particular bit becomes true, the bit sets to 1. When the condition becomes false, the bit resets to 0.
Monitoring Whether a Condition (Bit) has Changed
The transition registers determine which bit transition (condition change) should be recorded as an event. The transitions can be positive to negative, negative to positive, or both. To monitor a certain condition, enable the bit associated with the condition in the associated positive and negative registers.
Once you have enabled a bit via the transition registers, the PXB monitors it for a change in its condition. If this change in condition occurs, the corresponding bit in the event register will be set to 1. When a bit becomes true (set to 1) in the event register, it stays set until the event register is read or is cleared. You can thus query the event register for a condition even if that condition no longer exists.
To clear the event register, query its contents or send the *CLS command, which clears all event registers.
Monitoring When a Condition (Bit) Changes
Once you enable a bit, the PXB monitors it for a change in its condition. The transition registers are preset to register positive transitions (a change going from 0 to 1). This can be changed so the selected bit is detected if it goes from true to false (negative transition), or if either transition occurs.
You can use either of two methods described below to access the information in status registers (both methods allow you to monitor one or more conditions).
The polling method
In the polling method, the PXB has a passive role. It tells the controller that conditions have changed only when the controller asks the right question. This is accomplished by a program loop that continually sends a query.
The polling method works well if you do not need to know about changes the moment they occur. Use polling in the following situations:
when you use a programming language/development environment or IO interface that does not support SRQ interrupts
when you want to write a simple, single-purpose program and don't want the added complexity of setting up an SRQ handler
The service request (SRQ) method
In the SRQ method (described in the following section), the PXB takes a more active role. It tells the controller when there has been a condition change without the controller asking. Use the SRQ method to detect changes using the polling method, where the program must repeatedly read the registers.
Use the SRQ method if you must know immediately when a condition changes. Use the SRQ method in the following situations:
when you need time-critical notification of changes
when you are monitoring more than one device that supports SRQs
when you need to have the controller do something else while waiting
The programming language, I/O interface, and programming environment must support SRQ interrupts (for example: BASIC or VISA used with GPIB and VXI-11 over the LAN). Using this method, you must do the following:
Determine which bit monitors the condition.
Send commands to enable the bit that monitors the condition (transition registers).
Send commands to enable the summary bits that report the condition (event enable registers).
Send commands to enable the status byte register to monitor the condition.
Enable the controller to respond to service requests.
The controller responds to the SRQ as soon as it occurs. As a result, the time the controller would otherwise have used to monitor the condition, as in a loop method, can be used to perform other tasks. The application determines how the controller responds to the SRQ.
When a condition changes and that condition has been enabled, the request service summary (RQS) bit in the status byte register is set. In order for the controller to respond to the change, the Service Request Enable Register needs to be enabled for the bit(s) that will trigger the SRQ.
The Service Request Enable Register lets you choose the bits in the Status Byte Register that will trigger a service request. Send the *SRE <num> command where <num> is the sum of the decimal values of the bits you want to enable.
For example, to enable bit 7 on the Status Byte Register (so that whenever the Standard Operation Status register summary bit is set to 1, a service request is generated) send the command *SRE 128.
The query command *SRE? returns the decimal value of the sum of the bits previously enabled with the *SRE <num> command.
To query the Status Byte Register, send the command *STB?. The response will be the decimal sum of the bits which are set to 1. For example, if bit 7 and bit 3 are set, the decimal sum will be 136 (bit 7 = 128 and bit 3 = 8).
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Multiple Status Byte Register bits can assert an SRQ, however only one bit at a time can set the RQS bit. All bits that are asserting an SRQ will be read as part of the status byte when it is queried or serial polled. |
The SRQ process asserts SRQ as true and sets the status byte’s RQS bit to 1. Both actions are necessary to inform the controller that the PXB requires service. Asserting SRQ informs the controller that some device on the bus requires service. Setting the RQS bit allows the controller to determine which PXB requires service.
This process is initiated if both of the following conditions are true:
The corresponding bit of the Service Request Enable Register is also set to 1.
The PXB does not have a service request pending.
A service request is considered to be pending between the time the PXB’s SRQ process is initiated and the time the controller reads the status byte register.
If a program enables the controller to detect and respond to service requests, it should instruct the controller to perform a serial poll when SRQ is true. Each device on the bus returns the contents of its status byte register in response to this poll. The device whose request service summary (RQS) bit is set to 1 is the device that requested service.
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When you read the PXB’s Status Byte Register with a serial poll, the RQS bit is reset to 0. Other bits in the register are not affected. |
Most monitoring of PXB conditions is done at the highest level using the IEEE 488.2 common commands listed below. You can set and query individual status registers using the commands in the STATus subsystem.
*CLS (clear status) clears the Status Byte Register by emptying the error queue and clearing all the event registers.
*ESE,*ESE? (event status enable) sets and queries the bits in the Standard Event Enable Register which is part of the Standard Event Status Group.
*ESR? (event status register) queries and clears the Standard Event Status Register which is part of the Standard Event Status Group.
*OPC,*OPC? (operation complete) sets bit #0 in the Standard Event Status Register to 1 when all commands have completed. The query stops any new commands from being processed until the current processing is complete, then returns a 1.
*PSC,*PSC? (power-on state clear) sets the power-on state so that it clears the Service Request Enable Register, the Standard Event Status Enable Register, and device-specific event enable registers at power on. The query returns the flag setting from the *PSC command.
*SRE,*SRE? (service request enable) sets and queries the value of the Service Request Enable Register.
*STB? (status byte) queries the value of the status byte register without erasing its contents.
:STATus:PRESet presets all transition filters, non-IEEE 488.2 enable registers, and error/event queue enable registers as shown in the table below.
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Value after
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:STATus:OPERation:ENABle |
0 |
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:STATus:OPERation:NTRansition |
0 |
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:STATus:OPERation:PTRransition |
32767 |
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:STATus:QUEStionable:CALibration:ENABle |
32767 |
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:STATus:QUEStionable:CALibration:NTRansition |
32767 |
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:STATus:QUEStionable:CALibration:PTRansition |
32767 |
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:STATus:QUEStionable:ENABle |
0 |
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:STATus:QUEStionable:NTRansition |
0 |
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:STATus:QUEStionable:PTRansition |
32767 |
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:STATus:QUEStionable:FREQuency:ENABle |
32767 |
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:STATus:QUEStionable:FREQuency:NTRansition |
32767 |
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:STATus:QUEStionable:FREQuency:PTRansition |
32767 |
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:STATus:QUEStionable:TEMPerature:ENABle |
32767 |
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:STATus:QUEStionable:TEMPerature:NTRansition |
32767 |
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:STATus:QUEStionable:TEMPerature:PTRansition |
32767 |
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:STATus:QUEStionable:POWer:ENABle |
32767 |
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:STATus:QUEStionable:POWer:NTRansition |
32767 |
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:STATus:QUEStionable:POWer:PTRansition |
32767 |
The Status Byte Group includes the Status Byte Register and the Service Request Enable Register shown below.
|
Bit |
Description |
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0,1 |
Unused. These bits are always set to 0. |
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2 |
Error/Event Queue Summary Bit. A 1 in this bit position indicates that the SCPI error queue is not empty. The SCPI error queue contains at least one error message. |
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3 |
Data Questionable Status Summary Bit. A 1 in this bit position indicates that the Data Questionable summary bit has been set. The Data Questionable Event Register can then be read to determine the specific condition that caused this bit to be set. |
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4 |
Message Available. A 1 in this bit position indicates that the PXB has data ready in the output queue. There are no lower status groups that provide input to this bit. |
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5 |
Standard Event Status Summary Bit. A 1 in this bit position indicates that the Standard Event summary bit has been set. The Standard Event Status Register can then be read to determine the specific event that caused this bit to be set. |
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6 |
Request Service (RQS) Summary Bit. A 1 in this bit position indicates that the PXB has at least one reason to require service. This bit is also called the Master Summary Status bit (MSS). The individual bits in the Status Byte are individually ANDed with their corresponding service request enable register, then each individual bit value is ORed and input to this bit. |
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7 |
Standard Operation Status Summary Bit. A 1 in this bit position indicates that the Standard Operation Status Group’s summary bit has been set. The Standard Operation Event Register can then be read to determine the specific condition that caused this bit to be set. |
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Query: |
*STB? |
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Response: |
The decimal sum of the bits set to 1 including the master summary status bit (MSS) bit 6. |
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Example: |
The decimal value 136 is returned when the MSS bit is set low (0). Decimal sum = 128 (bit 7) + 8 (bit 3) The decimal value 200 is returned when the MSS bit is set high (1). Decimal sum = 128 (bit 7) + 8 (bit 3) + 64 (MSS bit) |
Service Request Enable Register
The Service Request Enable Register lets you choose which bits in the Status Byte Register trigger a service request.
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*SRE <data> |
<data> is the sum of the decimal values of the bits you want to enable except bit 6. Bit 6 cannot be enabled on this register. |
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Example: |
To enable bits 7 and 5 to trigger a service request when either corresponding status group register summary bit sets to 1, send the command *SRE 160 (128 + 32). |
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Query: |
*SRE? |
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Response: |
The decimal value of the sum of the bits previously enabled with the *SRE <data> command. |
The Standard Operation Status Group and the Data Questionable Status Group consist of the registers listed below. The Standard Event Status Group is similar but does not have negative or positive transition filters or a condition register.
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Condition |
A condition register continuously monitors the hardware and firmware status of the PXB. There is no latching or buffering for a condition register; it is updated in real time. |
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Negative |
A negative transition filter specifies the bits in the condition register that will set corresponding bits in the event register when the condition bit changes from 1 to 0. |
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Positive |
A positive transition filter specifies the bits in the condition register that will set corresponding bits in the event register when the condition bit changes from 0 to 1. |
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Event |
An event register latches transition events from the condition register as specified by the positive and negative transition filters. Once the bits in the event register are set, they remain set until cleared by either querying the register contents or sending the *CLS command. |
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Event |
An enable register specifies the bits in the event register that generate the summary bit. The PXB logically ANDs corresponding bits in the event and enable registers and ORs all the resulting bits to produce a summary bit. Summary bits are, in turn, used by the Status Byte Register. |
A status group is a set of related registers whose contents are programmed to produce status summary bits. In each status group, corresponding bits in the condition register are filtered by the negative and positive transition filters and stored in the event register. The contents of the event register are logically ANDed with the contents of the enable register and the result is logically ORed to produce a status summary bit in the Status Byte Register.
The Standard Event Status Group is used to determine the specific event that set bit 5 in the Status Byte Register. This group consists of the Standard Event Status Register (an event register) and the Standard Event Status Enable Register.
Standard Event Status Register
|
Bit |
Description |
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0 |
Operation Complete. A 1 in this bit position indicates that all pending PXB operations were completed following execution of the *OPC command. |
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1 |
Request Control. This bit is always set to 0. (The PXB does not request control.) |
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2 |
Query Error. A 1 in this bit position indicates that a query error has occurred. Query errors have instrument error numbers from –499 to –400. |
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3 |
Device Dependent Error. A 1 in this bit position indicates that a device dependent error has occurred. Device dependent errors have instrument error numbers from –399 to –300 and 1 to 32767. |
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4 |
Execution Error. A 1 in this bit position indicates that an execution error has occurred. Execution errors have instrument error numbers from –299 to –200. |
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5 |
Command Error. A 1 in this bit position indicates that a command error has occurred. Command errors have instrument error numbers from –199 to –100. |
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6 |
User Request Key (Local). A 1 in this bit position indicates that the Local key has been pressed. This is true even if the PXB is in local lockout mode. |
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7 |
Power On. A 1 in this bit position indicates that the PXB has been turned off and then on. |
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Query: |
*ESR? |
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Response: |
The decimal sum of the bits set to 1 |
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Example: |
The decimal value 136 is returned. The decimal sum = 128 (bit 7) + 8 (bit 3). |
Standard Event Status Enable Register
The Standard Event Status Enable Register lets you choose which bits in the Standard Event Status Register set the summary bit (bit 5 of the Status Byte Register) to 1.
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*ESE <data> |
<data> is the sum of the decimal values of the bits you want to enable. |
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Example: |
To enable bit 7 and bit 6 so that whenever either of those bits are set to 1, the Standard Event Status summary bit of the Status Byte Register is set to 1. Send the command *ESE 192 (128 + 64). |
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Query: |
*ESE? |
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Response: |
Decimal value of the sum of the bits previously enabled with the *ESE <data> command. |
The Operation Status Group is used to determine the specific event that set bit 7 in the Status Byte Register. This group consists of the Standard Operation Condition Register, the Standard Operation Transition Filters (negative and positive), the Standard Operation Event Register, and the Standard Operation Event Enable Register.
Standard Operation Condition Register
The Standard Operation Condition Register continuously monitors the hardware and firmware status of the PXB. Condition registers are read only.
|
Bit |
Description |
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0 |
Unused. These bits are always set to 0. |
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1 |
Reserved for future use. |
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2 |
Unused. These bits are always set to 0. |
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3 |
Reserved for future use. |
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4 |
Reserved for future use. |
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5 |
Waiting for Trigger. A 1 in this bit position indicates that the source is in a "wait for trigger” state. |
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6 |
Unused. These bits are always set to 0. |
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7 |
Unused. These bits are always set to 0. |
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8 |
Downloading. A 1 in this bit position indicates that the PXB is in the process of downloading a waveform. |
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9 |
System Playing. A 1 in this bit position indicates that the PXB is in the process of playing a waveform. |
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10 |
Reserved for future use. |
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11 |
Self Test Running. A 1 in this bit position indicates that the PXB is in the process of running self tests. |
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12 |
Reserved for future use. |
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13 |
Unused. These bits are always set to 0. |
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14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
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Query: |
STATus:OPERation:CONDition? |
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Response: |
The decimal sum of the bits set to 1 |
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Example: |
The decimal value 520 is returned. The decimal sum = 512 (bit 9) + 8 (bit 3). |
Standard Operation Transition Filters (negative and positive)
The Standard Operation Transition Filters specify which types of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands: |
STATus:OPERation:NTRansition
<value> (negative transition), or STATus:OPERation:PTRansition
<value> (positive transition), where
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Queries: |
STATus:OPERation:NTRansition? |
Standard Operation Event Register
The Standard Operation Event Register latches transition events from the condition register as specified by the transition filters. Event registers are destructive read only. Reading data from an event register clears the content of that register.
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Query: |
STATus:OPERation[:EVENt]? |
Standard Operation Event Enable Register
The Standard Operation Event Enable Register lets you choose which bits in the Standard Operation Event Register set the summary bit (bit 7 of the Status Byte Register) to 1.
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Command: |
STATus:OPERation:ENABle
<value>, where |
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Example: |
To enable bit 9 and bit 3 so that whenever either of those bits are set to 1, the Standard Operation Status summary bit of the Status Byte Register is set to 1, send the command STAT:OPER:ENAB 520 (512 + 8). |
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Query: |
STATus:OPERation:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:OPERation:ENABle <value> command. |
The Data Questionable Status Group is used to determine the specific event that set bit 3 in the Status Byte Register. This group consists of the Data Questionable Condition Register, the Data Questionable Transition Filters (negative and positive), the Data Questionable Event Register, and the Data Questionable Event Enable Register.
Data Questionable Condition Register
The Data Questionable Condition Register continuously
monitors the hardware and firmware status of the PXB. Condition registers
are read only.
|
Bit |
Description |
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0 |
Unused. These bits are always set to 0. |
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1 |
Unused. These bits are always set to 0. |
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2 |
Unused. These bits are always set to 0. |
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3 |
Power (summary). A 1 in this bit position indicates that one of its values is set to 1. |
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4 |
Temperature (summary). A 1 in this bit position indicates that one of its values is set to 1. |
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5 |
Frequency (summary). A 1 in this bit position indicates that one of its values is set to 1. |
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6 |
Unused. These bits are always set to 0. |
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7 |
Reserved for future use. |
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8 |
Calibration (summary). A 1 in this bit position indicates that one of its values is set to 1. |
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9 |
Self Test (power on). A 1 in this bit position indicates that there was an error during power on self test. |
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10 |
Self Test (user initiated). A 1 in this bit position indicates that there was an error during user initiated self test. |
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11 |
Unused. These bits are always set to 0. |
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12 |
Reserved for future use. |
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13 |
Unused. These bits are always set to 0. |
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14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
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Query: |
STATus:QUEStionable:CONDition? |
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Response: |
The decimal sum of the bits set to 1 |
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Example: |
This query returns the decimal sum of the bits for the registers that are set to one and are part of the Standard Operation Status Group. For example, if the waveform is downloading (bit 8), the value 256 is returned. The data in this register is continuously updated and reflect the current conditions. |
Data Questionable Transition Filters (negative and positive)
The Data Questionable Transition Filters specify which type of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands: |
STATus:QUEStionable:NTRansition
<value> (negative transition), or STATus:QUEStionable:PTRansition
<value> (positive transition), where
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Queries: |
STATus:QUEStionable:NTRansition? |
Data Questionable Event Register
The Data Questionable Event Register latches transition events from the condition register as specified by the transition filters. Event registers are destructive read-only. Reading data from an event register clears the content of that register.
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Query: |
STATus:QUEStionable[:EVENt]? |
Data Questionable Event Enable Register
The Data Questionable Event Enable Register lets you choose which bits in the Data Questionable Event Register set the summary bit (bit 3 of the Status Byte Register) to 1.
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Command: |
STATus:QUEStionable:ENABle <value> where <value> is the sum of the decimal values of the bits you want to enable. |
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Example: |
Enable bit 9 and bit 3 so that whenever either of those bits are set to 1, the Data Questionable Status summary bit of the Status Byte Register is set to 1. Send the command STAT:QUES:ENAB 520 (512 + 8). |
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Query: |
STATus:QUEStionable:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:QUEStionable:ENABle <value> command. |
The Power Questionable Status Group is used to determine the specific event that set bit 3 in the Data Questionable Condition Register. This group consists of the Power Questionable Condition Register, the Power Questionable Transition Filters (negative and positive), the Power Questionable Event Register, and the Power Questionable Event Enable Register.
Power Questionable Condition Register
The Power Questionable Condition Register continuously monitors the hardware and firmware status of the PXB. Condition registers are read only.
|
Bit |
Description |
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0 |
Reserved for future use. |
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1 |
Reserved for future use. |
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2 |
Reserved for future use. |
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3 |
Reserved for future use. |
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4 |
Power Calibration Failed. A 1 in this bit position indicates that the power calibration has failed. |
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5-14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
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Query: |
STATus:QUEStionable:POWer:CONDition? |
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Response: |
The decimal sum of the bits set to 1. |
Power Questionable Transition Filters (negative and positive)
The Data Questionable Power Transition Filters specify which type of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands: |
STATus:QUEStionable:POWer:NTRansition <value> (negative transition), or STATus:QUEStionable:POWer:PTRansition <value> (positive transition), where <value> is the sum of the decimal values of the bits you want to enable. |
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Queries: |
STATus:QUEStionable:POWer:NTRansition? STATus:QUEStionable:POWer:PTRansition? |
Power Questionable Event Register
The Data Questionable Power Event Register latches transition events from the condition register as specified by the transition filters. Event registers are destructive read-only. Reading data from an event register clears the content of that register.
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Query: |
STATus:QUEStionable:POWer[:EVENt]? |
Power Questionable Event Enable Register
The Power Questionable Event Enable Register lets you choose which bits in the Power Questionable Event Register set the summary bit (bit 3 of the Data Questionable Condition Register) to 1.
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Command: |
STATus:QUEStionable:POWer:ENABle <value> where <value> is the sum of the decimal values of the bits you want to enable |
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Example: |
Enable bit 3 and bit 2 so that whenever either of those bits are set to 1, the Data Questionable Power summary bit of the Data Questionable Condition Register is set to 1. Send the command STAT:QUES:POW:ENAB 12 (8 + 4). |
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Query: |
STATus:QUEStionable:POWer:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:QUEStionable:POWer:ENABle <value> command. |
The Data Questionable Frequency Status Group is used to determine the specific event that set bit 5 in the Data Questionable Condition Register. This group consists of the Frequency Questionable Condition Register, the Frequency Questionable Transition Filters (negative and positive), the Frequency Questionable Event Register, and the Frequency Questionable Event Enable Register.
Frequency Questionable Condition Register
The Frequency Questionable Condition Register continuously monitors the hardware and firmware status of the PXB. Condition registers are read-only.
|
Bit |
Description |
|
0 |
Reserved for future use. |
|
1 |
10 MHz Ref Unlocked. A 1 in this bit position indicates that the 10 MHz reference signal is unlocked. |
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2 |
Reserved for future use. |
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3 |
Reserved for future use. |
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4 |
Unused. This bit is always set to 0. |
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5 |
Reserved for future use. |
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6 |
Reserved for future use. |
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7-14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
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Query: |
STATus:QUEStionable:FREQuency:CONDition? |
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Response: |
The decimal sum of the bits set to 1. |
Frequency Questionable Transition Filters (negative and positive)
Specifies which types of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands: |
STATus:QUEStionable:FREQuency:NTRansition <value> (negative transition) or STATus:QUEStionable:FREQuency:PTRansition <value> (positive transition) where <value> is the sum of the decimal values of the bits you want to enable. |
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Queries: |
STATus:QUEStionable:FREQuency:NTRansition? |
Frequency Questionable Event Register
Latches transition events from the condition register as specified by the transition filters. Event registers are destructive read-only. Reading data from an event register clears the content of that register.
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Query: |
STATus:QUEStionable:FREQuency[:EVENt]? |
Frequency Questionable Event Enable Register
Lets you choose which bits in the Frequency Questionable Event Register set the summary bit (bit 5 of the Data Questionable Condition Register) to 1.
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Command: |
STATus:QUEStionable:FREQuency:ENABle <value>, where <value> is the sum of the decimal values of the bits you want to enable. |
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Example: |
Enable bit 4 and bit 3 so that whenever either of those bits are set to 1, the Data Questionable Frequency summary bit of the Data Questionable Condition Register is set to 1. Send the command STAT:QUES:FREQ:ENAB 24 (16 + 8). |
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Query: |
STATus:QUEStionable:FREQuency:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:QUEStionable:FREQuency:ENABle <value> command. |
The Temperature Questionable Status Group is used to determine the specific event that set bit 4 in the Data Questionable Condition Register. This group consists of the Temperature Questionable Condition Register, the Temperature Questionable Transition Filters (negative and positive), the Temperature Questionable Event Register, and the Temperature Questionable Event Enable Register.
Temperature Questionable Condition Register
The Temperature Questionable Condition Register continuously monitors the hardware and firmware status of the PXB. Condition registers are read-only.
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Bit |
Description |
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0 |
Fans Stopped. A 1 in this bit position indicates that the internal PXB fans have stopped. |
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1 |
Reserved for future use. |
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2 |
Ambient Temperature Too High. A 1 in this bit position indicates that the ambient temperature is too high and could cause the PXB to shut down. |
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3-14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
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Query: |
STATus:QUEStionable:TEMPerature:CONDition? |
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Response: |
The decimal sum of the bits set to 1. |
Temperature Questionable Transition Filters (negative and positive)
Specifies which types of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands: |
STATus:QUEStionable:TEMPerature:NTRansition <value> (negative transition), or STATus:QUEStionable:TEMPerature:PTRansition <value> (positive transition), where <value> is the sum of the decimal values of the bits you want to enable. |
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Queries: |
STATus:QUEStionable:TEMPerature:NTRansition? STATus:QUEStionable:TEMPerature:PTRansition? |
Temperature Questionable Event Register
Latches transition events from the condition register as specified by the transition filters. Event registers are destructive read-only. Reading data from an event register clears the content of that register.
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Query: |
STATus:QUEStionable:TEMPerature[:EVENt]? |
Temperature Questionable Event Enable Register
Lets you choose which bits in the Temperature Questionable Event Register set the summary bit (bit 4 of the Data Questionable Condition Register) to 1.
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Command: |
STATus:QUEStionable:TEMPerature:ENABle <value>, where <value> is the sum of the decimal values of the bits you want to enable. |
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Example: |
Enable bit 2 and bit 0 so that whenever either of those bits are set to 1, the Data Questionable Temperature summary bit of the Data Questionable Condition Register is set to 1. Send the command STAT:QUES:TEMP:ENAB 5 (4 + 1). |
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Query: |
STATus:QUEStionable:TEMPerature:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:QUEStionable:TEMPerature:ENABle <value> command. |
The Calibration Questionable Status Group is used to determine the specific event that set bit 8 in the Data Questionable Condition Register. This group consists of the Calibration Questionable Condition Register, Calibration Questionable Transition Filters (negative and positive), Calibration Questionable Event Register, Calibration Questionable Event Enable Register.
Calibration Questionable Condition Register
The Calibration Questionable Condition Register continuously monitors the calibration status of the PXB. Condition registers are read only.
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Bit |
Description |
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0 |
I/Q Calibration Failure. A 1 in this bit position indicates that the I/Q modulation calibration experienced a failure. |
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1-14 |
Unused. These bits are always set to 0. |
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15 |
Always 0. |
Calibration Questionable Transition Filters (negative and positive)
The Calibration Questionable Transition Filters specify which type of bit state changes in the condition register set corresponding bits in the event register. Changes can be positive (0 to 1) or negative (1 to 0).
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Commands |
STATus:QUEStionable:CALibration:NTRansition <value> (negative transition), or STATus:QUEStionable:CALibration:PTRansition <value> (positive transition), where <value> is the sum of the decimal values of the bits you want to enable. |
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Queries |
STATus:QUEStionable:CALibration:NTRansition? STATus:QUEStionable:CALibration:PTRansition? |
Calibration Questionable Event Register
The Calibration Questionable Event Register latches transition events from the condition register as specified by the transition filters. Event registers are destructive read-only. Reading data from an event register clears the content of that register.
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Query: |
STATus:QUEStionable:CALibration[:EVENt]? |
Calibration Questionable Event Enable Register
The Calibration Questionable Event Enable Register lets you choose which bits in the Calibration Questionable Event Register set the summary bit (bit 8 of the Data Questionable Condition register) to 1.
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Command: |
STATus:QUEStionable:CALibration:ENABle <value>, where <value> is the sum of the decimal values of the bits you want to enable. |
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Example: |
Enable bit 1 and bit 0 so that whenever either of those bits are set to 1, the Data Questionable Calibration summary bit of the Data Questionable Condition Register is set to 1. Send the command STAT:QUES:CAL:ENAB 3 (2 + 1). |
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Query: |
STATus:QUEStionable:CALibration:ENABle? |
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Response: |
Decimal value of the sum of the bits previously enabled with the STATus:QUEStionable:CALibration:ENABle <value> command. |
