Standard Event Register

The following table describes the Standard Event Register.

0	Operation Complete	1	All commands prior to and including *OPC have been executed.
1		2
2	Query Error	4	The instrument tried to read the output buffer but it was empty. Or, a new command line was received before a previous query has been read. Or, both the input and output buffers are full.
3	Device-Specific Error	8	A device-specific error, including a self-test error or calibration error, occurred (an error in the -300 range or any positive error has been generated).
4	Execution Error	16	An execution error occurred (an error in the -200 range has been generated).
5	Command Error	32	A command syntax error occurred (an error in the -100 range has been generated).
6		64
7	Power On	128	Power has been cycled since the last time the event register was read or cleared.

Status Byte Register

The following table describes the Status Byte Register.

0		1
1		2
2		4	One or more errors have been stored in the . Use SYSTem:ERRor? to read and delete errors.
3	Questionable Data Summary	8	One or more bits are set in the Questionable Data Register (bits must be enabled, see STATus:QUEStionable:ENABle).
4	Message Available	16	Data is available in the instrument's output buffer.
5	Standard Event Summary	32	One or more bits are set in the Standard Event Register (bits must be enabled, see *ESE).
6	Master Summary	64	One or more bits are set in the Status Byte Register and may generate a Request for Service (RQS). Bits must be enabled using *SRE.
7	Standard Operation Summary	128	One or more bits are set in the Standard Operation Register (bits must be enabled, see STATus:OPERation:ENABle).

Calibration Query. Peforms autocalibration (autocal) and returns the result.

	+0 (no error) +1 (cal error)
Perform autocalibration, return result: *CAL?

Clear Status Command. Clears the event registers in all register groups. Also clears the error queue.

Clear event register bits and error queue:

Event Status Enable Command and Query. Enables bits in the enable register for the Standard Event Register group. The selected bits are then reported to bit 5 of the Status Byte Register.

	+48

• Use *PSC to control whether the Standard Event enable register is cleared at power on.

Standard Event Status Register Query. Queries the event register for the Standard Event Register group.

	+24
Read the event register (bits 3 and 4 are set):

• In order to be reported to the Status Byte Register, the corresponding bits in the enable register must be enabled by *ESE.
• Any or all conditions can be reported to the Standard Event summary bit through the enable register. To set the enable register mask, write a decimal value to the register using *ESE.

Identification Query. Returns the instrument’s identification string.

Return the instrument's identification string:

• For firmware revisions prior to 2.0, the identification string contains these four comma separated fields:
  
  Manufacturer name, Model number, Serial number, Revision code
  
  
  
  If SYSTem:IDENtify HP34401A is set, the returned string has the following format:
  
  HEWLETT-PACKARD,34401A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  
  Where:
  h. - Hardware revision
  ff.ff - Main firmware revision
  pp.pp - Front panel firmware revision
  mm.mm - Measurement board firmware revision
  gg.gg - Measurement board FPGA revision
  bb - Measurement board revision
  fp - Front panel board revision
  
  

• For firmware revision 2.0 and later, the identification string contains these four comma separated fields:
  
  Manufacturer name, Model number, Serial number, Revision code
  
  If SYSTem:IDENtify DEFault is set, the returned string has the following format:
  
  Keysight Technologies,34460A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  Keysight Technologies,34461A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  Keysight Technologies,34465A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  Keysight Technologies,34470A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  
  
  
  If SYSTem:IDENtify HP34401A is set, the returned string has the following format:
  
  HEWLETT-PACKARD,34401A,<Serial Number>,h.ff.ff-pp.pp-mm.mm-gg.gg-bb-fp
  
  
  Where:
  h. - Hardware revision
  ff.ff - Main firmware revision
  pp.pp - Front panel firmware revision
  mm.mm - Measurement board firmware revision
  gg.gg - Measurement board FPGA revision
  bb - Measurement board revision
  fp - Front panel board revision

Returns an ASCII string of all of the commands required to put the instrument into its current state.

	An ASCII string of SCPI commands, delimited with semicolons (";") between commands.
Return the learn string:

• Some parameters can be set with either [SENSe:]FREQuency or [SENSe:]PERiod versions of the same command. The *LRN string always returns the FREQuency version of the command, even if the parameter was set via the PERiod version. Similarly, parameters that can be set with RESistance or FRESistance versions of the same command always return the FRESistance version.

Sets "Operation Complete" (bit 0) in the Standard Event register at the completion of the current operation.

• Other commands may be executed before Operation Complete bit is set.

Returns 1 to the output buffer after all pending commands complete. Other commands cannot be executed until this command completes.

	1
Configure 100 DC voltage measurements and return "1" when the measurements complete: SAMP:COUN 100 INIT

• Use this command to synchronize your application with the instrument.

Returns a string identifying any installed options.

Return the installed options:

• This query returns a string with the following format:
  
  34460A: {GPB|0},{LAN|0},{SEC|0}
  34461A: {GPB|0},{SEC|0}
  34465A/70A: {GPB|0},{SEC|0},{DIG|0},{MEM|0}
  
  A 0 is returned for options that are not installed. For example, a 34461A with only GPIB installed returns GPB,0. A 34460A with only GPB and SEC installed returns GPB,0,SEC.
• Options vary by model, as shown here.

Power-On Status Clear. Enables (1) or disables (0) the clearing of certain enable registers at power on:

• Questionable Data Register (STATus:QUEStionable:ENABle)
• Standard Operation Register (STATus:OPERation:ENABle)
• Status Byte Condition Register (*SRE)
• Standard Event Enable Register (*ESE)

The *PSC command does not affect the clearing of the condition or event registers, just the enable registers.

. Default: 1	0 or 1
Disable power-on clearing of affected registers: 0

Stores the current instrument state to, or recalls the instrument state from, the state file STATE_<n>.sta in the root folder of the internal flash file system, where <n> is the number specified.

Store the instrument state to the state file STATE_1.sta in the root folder of the internal flash file system: 1

• *SAV <n> is equivalent to MMEMory:STORe:STATe "INT:\STATE_n.sta".
• *RCL <n> is equivalent to MMEMory:LOAD:STATe "INT:\STATE_n.sta".
• The instrument state enable settings are stored in nonvolatile memory.

Resets instrument to factory default state. This is similar to SYSTem:PRESet.

Reset the instrument:

• Does not affect stored instrument states (see ).

Service Request Enable. Enables bits in the enable register for the Status Byte Register group.

	+24
Enable bits 3 and 4 in the enable register: 24

• To enable specific bits, specify the decimal value corresponding to the binary-weighted sum of the bits in the register. The selected bits are summarized in the "Master Summary" bit (bit 6) of the Status Byte Register. If any of the selected bits change from 0 to 1, the instrument generates a Service Request signal.
• *PSC (power-on status clear) determines whether Status Byte enable register is cleared at power on.
• The Status Byte enable register is not cleared by *RST.

Read Status Byte Query. Queries the condition register for the Status Byte Register group and returns a decimal value equal to the binary-weighted sum of all bits set in the register.

	+40
Read condition register (with bits 3 and 5 set):

• Similar to a Serial Poll, but processed like any other instrument command.
• Returns same result as a Serial Poll, but the "Master Summary" bit (bit 6) is not cleared by *STB?.
• Power cycle and *RST clear all bits in the condition register.

Triggers the instrument if TRIGger:SOURce BUS is selected.

TRIG:SOUR BUS INIT FETCH? +1.00520000E+01, … (5 measurements)

• After setting the trigger source, you must send INITiate to place the DMM in the "wait-for-trigger" state. The *TRG command is not accepted unless the DMM is in the "wait-for-trigger" state.

Performs a basic self-test of the instrument and returns a pass/fail indication.

Perform self-test:

• The self-test takes just a few seconds to complete.

Configures the instrument's output buffer to wait for all pending operations to complete before executing any additional commands over the interface.

Wait until all pending operations complete:

• Configuration changes and measurements are considered pending operations. Therefore, *WAI causes these changes to occur and complete.