The following table lists the bit definitions for the Questionable Data Register:
|
The overload bits are set once per INITiate command. If you clear an overload bit, it is not set again until a new INITiate is sent. |
|
Bit Number |
Bit Name |
Decimal Value | Definition |
|---|---|---|---|
|
0 |
Voltage Overload |
1 |
Only reported as event. Returns 0. Read the Event Register. |
|
1 |
Current Overload |
2 |
Only reported as event. Returns 0. Read the Event Register. |
|
2 |
Sample Timing Violation |
4 |
A sample timing violation has occurred involving the SAMPle:TIMer command. Sample timing may not be valid. Applies only to the 34465A and 34470A. |
|
3 |
Not Used |
8 |
(Reserved for future use) |
|
4 |
Temperature Overload |
16 |
Only reported as event. Returns 0. Read the Event Register. |
|
5 |
Frequency Overload/Underflow |
32 |
Only reported as event. Returns 0. Read the Event Register. |
|
6 |
Not Used |
64 |
(Reserved for future use) |
|
7 |
Not Used |
128 |
(Reserved for future use) |
|
8 |
Calibration Corrupt |
256 |
At least one calibration constant is corrupt. |
|
9 |
Resistance Overload |
512 |
Only reported as event. Returns 0. Read the Event Register. |
|
10 |
Capacitance Overload |
1024 |
Only reported as event. Returns 0. Read the Event Register. |
|
11 |
Lower Limit Failed |
2048 |
The most recent measurement failed the lower limit test. |
|
12 |
Upper Limit Failed |
4096 |
The most recent measurement failed the upper limit test. |
|
13 |
Not Used |
8192 |
(Reserved for future use) |
|
14 |
Memory Overflow |
16384 |
Reading memory is full. One or more (oldest) measurements have been lost. |
|
15 |
Not Used |
32768 |
(Reserved for future use) |
The following table lists the bit definitions for the Standard Operation Register:
|
Bit Number |
Bit Name |
Decimal Value | Definition |
|---|---|---|---|
|
0 |
Calibrating |
1 |
Instrument is performing a calibration. |
|
1 |
Not Used |
2 |
(Reserved for future use) |
|
2 |
Not Used |
4 |
(Reserved for future use) |
|
3 |
Not Used |
8 |
(Reserved for future use) |
|
4 |
Measuring |
16 |
Instrument is initiated, and is making or about to make a measurement. |
|
5 |
Waiting for Trigger |
32 |
Instrument is waiting for a trigger. |
|
6 |
Not Used |
64 |
(Reserved for future use) |
|
7 |
Not Used |
128 |
(Reserved for future use) |
|
8 |
Configuration Change |
256 |
Instrument configuration has been changed since the last INIT, READ? or MEASure?, either from the front panel or from SCPI. |
|
9 |
Memory Threshold |
512 |
Programmed number of measurements (DATA:POINts:EVENt:THReshold) have been stored in measurement memory. |
|
10 |
Instrument Locked |
1024 |
Set if a remote interface (GPIB, USB or LAN) has a lock (SYSTem:LOCK:REQuest?). Cleared when the remote interface releases the lock (SYSTem:LOCK:RELease). |
|
11 |
Not Used |
2048 |
(Reserved for future use) |
|
12 |
Not Used |
4096 |
(Reserved for future use) |
|
13 |
Global Error |
8192 |
Set if any remote interface has an error in its error queue; cleared otherwise. |
|
14 |
Not Used |
16384 |
(Reserved for future use) |
|
15 |
Not Used |
32768 |
"0" is returned. |
Returns the sum of the bits in the condition register for the Standard Operation Register group. This register is read-only; bits are not cleared when read.
A condition register continuously monitors the state of the instrument. Condition register bits are updated in real time; they are neither latched nor buffered.
| Parameter | Typical Return |
|---|---|
| (none) | +32 |
| Read the condition register (bit 5 is set): STAT:OPER:COND? |
|
Enables bits in the enable register for the Standard Operation Register group. The selected bits are then reported to the Status Byte. An enable register defines which bits in the event register will be reported to the Status Byte register group. You can write to or read from an enable register.
| Parameter | Typical Return |
|---|---|
| A decimal value that corresponds to the binary-weighted sum of the bits in the register. | +32 |
| Enable bit 5 (decimal value 32) in the enable register: STAT:OPER:ENAB 32 |
|
Returns the sum of the bits in the event register for the Standard Operation Register group. An event register is a read-only register that latches events from the condition register. While an event bit is set, subsequent events corresponding to that bit are ignored. The register bits are cleared when you read the register.
| Parameter | Typical Return |
|---|---|
| (none) | +512 |
| Read the event register (bit 9 is set): STAT:OPER:EVEN? |
|
Clears Questionable Data enable register and Standard Operation enable register.
| Parameter | Typical Return |
|---|---|
| (none) | (none) |
| Clear enable register bits: STAT:PRES |
|
Returns the sum of the bits in the condition register for the Questionable Data Register group. This register is read-only; bits are not cleared when read.
A condition register continuously monitors the state of the instrument. Condition register bits are updated in real time; they are neither latched nor buffered.
| Parameter | Typical Return |
|---|---|
| (none) | +4096 |
| Read the condition register (bit 12 is set): STAT:QUES:COND? |
|
Enables bits in the enable register for the Questionable Data Register group. The selected bits are then reported to the Status Byte. An enable register defines which bits in the event register will be reported to the Status Byte register group. You can write to or read from an enable register.
| Parameter | Typical Return |
|---|---|
| A decimal value that corresponds to the binary-weighted sum of the bits in the register. | +512 |
| Enable bit 9 (decimal value 512) in the enable register. | |
Returns the event register for the Questionable Data Register group. An event register is a read-only register that latches events from the condition register. While an event bit is set, subsequent events corresponding to that bit are ignored. The register bits are cleared when you read the register.
| Parameter | Typical Return |
|---|---|
| (none) | +1024 |
| Read the event register (bit 10 is set): STAT:QUES? |
|